module memory_bank
#(
  parameter DATA_SIZE = 32,               //Memory data word width
  parameter ADDR_SIZE = 2                 //Number of memory address bits
)(
  //OUTPUTS
  output [DATA_SIZE - 1:0] data_out,      //Data to be read
  //INPUTS
  input  [DATA_SIZE - 1:0] data_in,       //Data to be written
  input  [ADDR_SIZE - 1:0] addr,          //read/write address
  input write_enable,                     //enables memory write
  input clk                               //Clock
);

localparam MEM_DEPTH = 1<<ADDR_SIZE;

reg [DATA_SIZE -1:0] mem_bank[0:MEM_DEPTH -1];

assign data_out = mem_bank[addr];

always @(posedge clk)
  begin
    if(write_enable) 
      mem_bank[addr] <= data_in;
  end
  
endmodule
